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Silicon Labs /EFR32MG24A020F1536IM40 /MODEM_NS /COH0

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Interpret as COH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (COHDYNAMICBBSSEN)COHDYNAMICBBSSEN 0 (COHDYNAMICSYNCTHRESH)COHDYNAMICSYNCTHRESH 0 (COHDYNAMICPRETHRESH)COHDYNAMICPRETHRESH 0 (TIMDET)COHCHPWRLOCK 0 (COHCHPWRRESTART)COHCHPWRRESTART 0 (SEL0)COHDYNAMICPRETHRESHSEL 0COHCHPWRTH00COHCHPWRTH10COHCHPWRTH2

COHCHPWRLOCK=TIMDET, COHDYNAMICPRETHRESHSEL=SEL0

Description

No Description

Fields

COHDYNAMICBBSSEN

Dynamic BBSS enable bit
COHDYNAMICSYNCTHRESH

Dynamic syncword threshold enable bit
COHDYNAMICPRETHRESH

Dynamic preamble threshold enable bit
COHCHPWRLOCK

Channel power lock

0 (TIMDET): Channel power locked when timing is detected

1 (DSADET): Channel power locked when DSA is detected
COHCHPWRRESTART

Channel power restart
COHDYNAMICPRETHRESHSEL

Dynamic preamble threshold selection

0 (SEL0): 1x sync coeff

1 (SEL1): 0.94x sync coeff

2 (SEL2): 0.88x sync coeff

3 (SEL3): 0.74x sync coeff

4 (SEL4): 0.5x sync coeff
COHCHPWRTH0

Channel power threshold
COHCHPWRTH1

Channel power threshold
COHCHPWRTH2

Channel power threshold

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data